A Monolithic 50-200 MHz CMOS Clock Recovery and Retiming Circuit

This circuit has been manufactured in a 0.9micron digital CMOS technology and will recover a clock from NRZ random data. Features of the chip include BIST, crystal or reference clock inputs, differential or single ended ECL 100k I/O. Typical performance yields an output jitter of 6.0degrees RMS for 2 sup 23 -1 pseudo-random data at 200 MHz.