A New Floorplan Representation for VLSI Design.
01 January 1987
A new and more robust floorplan representation is introduced and its properties are studied in this paper. We proved that this representation is unambiguous for aryclic floorplans. It is also proved that for a given problem, the number of forks, the number of faces, and the number of edges in this representation are all constants, independent of the topological arrangements of the modules. These properties can help us reduce the search space and lend this representation to coherent design and easy development of a powerful set of floorplanning tools. Currently, based on this representation, a set of tools, Fork, are being developed for supporting structural constraints, achieving better global optimization, and supporting interactive design.