A new multi-core software architecture for improving CUR in LTE Layer1 DSP/SoC

Multi-core digital signal processor (DSP) and system on chip (SoC) are widely used in Long Term Evolution (LTE) L1 development since 5 years ago. The corresponding multi-core software architecture design is a big challenge. Nowadays, a traditional 3 layers architecture is very popular. Its 3 layers are accelerators driver layer, OS layer and application layer. One shortage of this architecture is the weak cross-vendor portability. A worse one is the low chip capability utilization rate (CUR) in some cases. In order to improve the CUR and simplify the cross-vendor porting, an improved hierarchy architecture is presented in this paper. Its 3 layers are different from the above traditional ones: the operating system (OS) layer, control process layer and user process layer. An Inter-Process Communication (IPC) module is newly added. In this proposed new architecture, the user process is separated from the control process. The global buffers are the bridges between these two layers, and could be shared by all the tasks on all cores. The common IPC supports transparent and flexible communication between all tasks on all cores. As a result, tasks can be dynamically mapped on cores at run time. Three improvements are obtained with this new architecture. 1) All the user process tasks can be flexibly adjusted among cores. The core load can be balanced very well in each scenario, so as to improve the CUR. 2) Almost all the control process tasks ( in C language ) can be directly reused on other venders¡¯ DSP/SoC. The cross-vendor porting is significantly simplified. 3) All layers can be developed in parallel to speed up the time to market (TTM) progress.