A new TTL-CMOS input buffer and an inverter with process independent threshold voltage.

This memo presents a new TTL-CMOS input buffer structure. We present two designs of this buffer - a speed optimized version, and a noise margin optimized version. The speed optimized buffer has a worst case delay of less than 3.3 ns driving an output load of up to 0.2 pF. The noise optimized buffer has more than 390 mV additional noise margin of both TTL "one" and "zero". These buffers are compared to two other existing buffers and are shown to have better performance and require less layout area for the same power dissipation. The new buffer can also be optimized to obtain high speed and high drive capability with minimal sacrifice in area and power. Furthermore, the first stage of this input buffer has an almost process independent threshold voltage for a particular size of the devices.