A pipelined 14-tap parallel decision-feedback decoder for 1000BASE-T Gigabit Ethernet

Parallel decision feedback decoding is the preferred algorithm for joint postcursor equalization and trellis decoding in 1000BASE-T Gigabit Ethernet, as it achieves most of the theoretically possible coding gain at a reasonable hardware complexity. However, the VLSI implementation of a 125 MHz, 14-tap parallel decision-feedback decoder (PDFD) is very challenging because of the critical path problem. This paper presents a pipelined 14-tap PDFD VLSI architecture for 1000BASE-T. The design is implemented in 3.3 V 0.16 μm standard cell CMOS process and operates at 125 MHz to achieve 1 Gb/s throughput. Compared to a conventional 14-tap PDFD implementation, the processing speed is improved by a factor of two