A programmable Digital Signal Processor with 32b floating point arithmetic.

A programmable DSP(TM) with 32b floating point arithmetic has been fabricated in 1.5micron (Leff) NMOS technology. The data path is 32b and the DSP implements an extensive 32b instruction set. The device contains 155,000 transistors and operates at a 16MHz clock frequency. Its dimensions are 12.70mm by 6.35mm. This device has the capability to cost-effectively realize complex applications such as speech recognition, high speed modems, very low bit rate speech CODECs and multichannel signaling systems. This memorandum is the manuscript of the DSP announcement submitted for publication in the 1985 IEEE International Solid-State Circuits conference Digest of Technical Papers.