A radix 2 shared division square root algorithm and its VLSI architecture

This paper presents the VLSI architecture of a shared division/square root operator that operates on the mantissas (23-b in length) of single precision IEEE 754 1985 std., floating point numbers. The division and square root algorithms used in this operator are based on radix 2 signed digit representations and operate in a digit-by-digit manner. These two algorithms perform quotient and root digit selection using two most-significant digits of the partial remainder. Previously proposed shared division square-root algorithms required more than two most-significant digits of the partial remainder to be observed during quotient or root digit selection. Lower the number of digits observed for quotient or root digit selection, faster the operation. Due to this, the algorithms proposed in this scheme are faster than previous schemes. This architecture has been layed out using 1.2 micron 5.0 V CMOS 2 metal process and requires 14.82 mm(2) area. This design requires 15 ns (@ 5.0 V) to generate a digit of the quotient/root. It requires 29 cycles per divide/square root operation from the time the operands are provided at its pin inputs.