A Reconfigurable, Fault-Tolerant Systolic Signal Processor

We describe a parallel computer architecture targeted at signal pattern analysis applications, scalable to configurations capable of TeraFLOP (10 sup 12 floating point operations per second) throughput. An important attribute of the architecture is its low interconnection overhead, making it well-suited to miniaturization via advanced packaging. Preliminary design and thermal tests project a computing density of 300 GigaFLOPS per cubic foot.