A Reconfiguration Scheme for Fault Tolerant Wafer Scale Arrays with Large PEs.

Fault tolerant architectures designed for yield enhancements are important to the eventual success of Wafer Scale Integration. Previously proposed architectures have tended to be aimed at arrays containing small processing elements only. Herein is described an architecture that is aimed at providing fault tolerance for mesh connected arrays containing medium to large size processing elements. This approach embeds each processing element in a "frame" of general soft switching elements. It is shown how this approach provides the required flexibility to efficiently use surviving processors whilst avoiding much of the complexity of computing the reconfiguration strategy.