A Self Aligned CoSi sub 2 Source/Drain/Gate Multi-Gigahertz Symmetric CMOS Technology (NOT PUBLISHED)

A 0.5microns CMOS technology has been developed that uses a silicided source/ drain/gate with CoSi sub 2. The n-channel and p-channel devices are symmetric in threshold voltages, vertical dimensions and channel lengths. This is accomplished by using a silicided n+ and p+ polysilicon gate structure and a shallow junction technique to allow both the NMOS and PMOS source/drain j junctions to be equally shallow.