A SiGe HBT BiCMOS 1-to-4 ADC frontend enabling low bandwidth digitization of 100 GBaud PAM4 data

Market forecasts for intra and inter data center interconnects predict high growth rates in the upcoming years. This is associat-ed with increasing requirements in terms of costs, power con-sumption and bit rate per wavelength. Today, PAM4 systems are frequently used at up to 100 Gb/s per wavelength. The next logi-cal step is to double the symbol rate to allow bit rates of 200 Gb/s at the same modulation format and at the same direct detection scheme. Such systems require three-digit gigasample analog-to-digital converters with bandwidths larger than 50 GHz, which are not available today as CMOS components. To extend the band-width of CMOS converters, we suggest the use of ADC frontends, which sample and demultiplex the analog input sig-nals simultaneously. At the outputs of such ADC frontends, the signals can then be digitized by parallel converters with lower bandwidth and at a lower conversion rate.