A Simple Embedded DRAM Process for 0.16microns CMOS Technologies

A typical embedded DRAM (eDRAM) process adds 6 to 9 additional lithographic steps to the core LOGIC process [1]. While eDRAM capacitors need only 2-3 steps, the rest are front-end related in order to minimize the total leakage current of storage-nodes and to improve the memory density. Fig.,1 shows a conventional process. Not only is it costly, it also leads to difficult topography and additional thermal cycles that modify the LOGIC FETs. The eDRAM areas use a separate S/D extension I/I different from the LOGIC areas. The regular deep-S/D I/I is blocked. Furnace poly-Si plugs [2-4] are used to make contacts, and an additional metal level (MTO) is used for bit line runners [2,3,5]. Consequently, high-aspect-ratio W-plugs and poly-Si plugs are both necessary in previously reported structures of COB (capacitor-over-bit-line) [2], CUB (capacitor-under-bit-line) [3], and COM (capacitor-over-metal) [4].