A Testable PLA Design with Low Overhead and Ease of Test Generation

This paper presents a new design of fully testable PLAs with extremely low overhead and ease of test generation. By adding only one MOS transistor switch to control each complement input bit line, Reddy and Ha [1] demonstrated a testable design of PLAs with minimal area penalty. However, the derivation of tests is not very simple and may depend on the synthesis procedure. Bozorgui-Nesbat [2] presented a partitioning method to reduce the overhead required for full testability. However, the overhead required by [2] is usually higher than the method proposed in [1] even though the overhead is significantly less than the overhead required by comparable PLA design-for-testability methods.