A unified circuit model for bipolar transistors, including quasi-saturation effects.

This memorandum describes a compact model for bipolar transistors which includes quasi-saturation effects. The assumptions used in the formulation of this model are clearly stated and justified, and a step by step derivation of the model equations is presented. These equations model both dc and charge storage effects. Parameter extraction techniques are qualitatively described and the compact model is evaluated using detailed physical simulations of a high voltage bipolar transistor. In addition, simulation employing this model are compared with measurements and are found to be in excellent agreement.