A video rate FIR filter chip: Design method.

In this memorandum we present the design method of an experimental video Finite Impulse Response (FIR) digital filter chip. This very high performance programmable digital FIR filter was designed in 0.9micron CMOS technology using the new IMPALA tool. The IMPALA method is unique because it allows for a mix of custom sized polycells and full custom circuits that were optimized with the TILOS transistor sizer program. IMPALA makes it possible to develop a completely custom circuit with individually sized transistors with the same ease and efficiency as was previously possible only with standard cells or gate arrays. The chip was designed both to evaluate IMPALA and to try out some of the architectures for application specific Digital Signal Processing (DSP) where testability and high throughput are the primary considerations.