Algorithms for Accuracy Enhancement in a Hardware Logic Simulator

Hardware simulators are becoming increasingly common in today's VLSI design environments. Earlier, we described the architecture and design of one such hardware accelerator, MARS (Microprogrammable Accelerator for Rapid Simulations) [ADE87], [ADF87]. In this paper, we focus on multiple delay logic simulation algorithms developed for MARS. In particular, timing analyses algorithms for event cancellations, spike and race analyses and oscillation detection are described in detail. We demonstrate how a reconfigurable set of processors, called processing elements (PEs) can be arranged in a pipelined configuration to implement these algorithms.