An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits

Multiple delay simulation [1] is an efficient way of providing the circuit designer with timing information about the circuit. In this mode of simulation, the output logic level transitions of a single occur with appropriate delay times that are computed automatically in the simulator. This paper describes the models and techniques used in the second generation MOTIS system [2] for delay characterization. The accuracy of these models is demonstrated by comparison with timing simulation [3,4,5] and is typically within 5% of timing simulation for most MOS digital circuits.