An ADPCM Approach to Reduce the Bit Rate of u-Law Encoded Speech

Bit rate reduction from the present 64 kb/s per trunk is of interest both to reduce per-trunk cost of existing and planned digital transmission facilities and to prove-in digital transmission. Adaptive differential PCM (ADPCM) coding of the type reported in Refs. 1 through 4 appears promising for bit rate reduction of speech signals. Our specific interest is the bit rate reduction of the conventional /x-255, 64-kb/s signal. The purpose of this paper is to present an A D P C M architecture that offers: (i) simple hardware realization, (ii) flexible algorithm modification, (iii) fixed hardware complexity with respect to numerous nonlinear processings, and (iv) time-sharing capability over many trunks. T h e performance of a hardware realization of such a coder, which is shared by 24 voice trunks, is also reported.