An Advanced Four Level Interconnect Enhancement Module for 0.9 Micron CMOS

In this paper we describe the demonstration of a four level interconnection enhancement of our 0.9 micron CMOS technology. The major features of this advanced interconnect are frameless contacts, stacked vias, and the maintenance of constant design rules throughout all four levels. The metal pitch is 2.20 micron with contact and via sizes of 1.0microns x 1.0microns. Each dielectric layer is planarized using resist etchback planarization. The windows and vias are filled using blanket tungsten etchback plugs.