An Automated BIST Approach for General Sequential Logic Synthesis

An automated Built-In Self-Test (BIST) technique for general sequential logic is described. This BIST approach has been incorporated in a behavioral model synthesis systems providing automated implementation of BIST in Very Large Scale Integration (VLSI) devices as well as Programmable Logic Device (PLD) based circuit packs. The BIST technique can be directly used at all levels of testing from device testing through system diagnostics. In addition, a partial scan design capability is provided at no extra expense in terms of logic overhead. Two production VLSI devices have been implemented with this automated BIST approach; fault coverage and logic overhead as a result of the BIST implementations will be reported.