An automatic rectilinear partitioning procedure for standard cells.

This memorandum describes a novel approach to automatically partition and place the standard cells on a chip among the pre-placed macro cells (RAM, ROM, PLA etc.) and I/O pads. The topological and physical constraints, and the net list connectivity are accounted for simultaneously. The locations of pre-seeded standard cells are respected. At the end of the procedure, the circuit is partitioned and the clusters of standard cells are placed. Unlike conventional min-cut partitioning programs that partition standard cells in a rectangular area, this procedure partitions standard cells within an arbitrary shape of rectilinear geometry to efficient use the available space on the chip.