An Economical Scan Design for Sequential Logic Test Generation

This paper presents a method of partial scan design in which the selection of scan flip-flops is aimed at breaking up the cyclic structure of the circuit. Experimental data are given to show that the test generation complexity may grow exponentially with the length of cycles in the circuit. This complexity grows only linearly with the sequential depth. Graph-theoretic algorithms are presented to select minimal sets of flip-flops for eliminating cycles and for reducing the sequential depth. Tests for the resulting circuit can be efficiently generated by a sequential test generator.