An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation

We developed a new method for partitioning (technology-mapped) circuits into multiple FPGAs. This method supports multiple classes of cells and, so, input circuits may contain different types of cells. It also supports different sizes of blocks (i.e., FPGAs) and pin limitation of each block. The method tries to minimize the total number of terminals of all blocks while satisfying the size and pin constraints of each block. The method makes use of a scalar value of benefit which captures lookahead information. As a result, it avoids the computation complexity of Sanchis [1] due to large gain vector, while it maintains lookahead capability.