An FPGA application with high speed serial transceiver running at sub nominal rate

We describe an implementation of the physical layer circuit for 100Mb/s optical Ethernet using an FPGA device with embedded high-speed serial transceivers. The design is the foundation for implementing a dual-speed 100/1000 Mb/s Ethernet system in which all components except the optical ones are implemented in an FPGA. The low-speed mode is outside the transceiver's nominal range, so the PLL circuit in the receiver cannot reliably lock to the received clock. 

We solve the problem by using the data recovery technique known as blind oversampling. The design can easily be adapted to implement other transmission systems that may put the operating point of the transceiver outside its nominal range, extending the scope of applications in which 'FPGA to the optics' approach is viable.