An Injection Locked 0.25 micron CMOS 5.6Gb/s Clock and Data Recovery Cell

A sub-harmonic clock signal in a 5.6 Gb/s NRZ (Non Return to Zero) 2 sup 7 -1 pseudo-random data stream is used to injection lock a CMOS LC tank circuit to 2.8GHz. The data stream is de-serialized into two 2.8Gb/s data streams by a parallel combination of a positive and negative edge flip-flops (FF) clocked with alternate edges of this recovered clock. A measured Bit Error Rate (BER) of less than 2E-13 at 5.6Gb/s is achieved using a conventional 0.25 micron CMOS technology.