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    An Optimal Test Sequence for the JTAG Boundary-Scan Controller

An Optimal Test Sequence for the JTAG Boundary-Scan Controller

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In this paper, a test sequence is given for the Test Access Port (TAP) controller portion of the boundary-scan architecture proposed by the Joint Test Action Group (JTAG) as an industry-standard design-for-testability technique. The resulting test sequence generated by using the POSTMAN package, a software tool based on Rural Chinese Postman tours and Unique Input/Output sequences [1], is of minimum-cost (time) and rigorously tests the specified functional behavior of the controller.