Analysis and Synthesis of a Digital Phase-Locked Loop for FM Demodulation

A new phase-locked loop (PLL) with interesting properties has been developed for potential application in large multiple data set installations which provide low speed serial data communications for time-shared computers. An objective for such data set arrangements is to minimize cost per channel by putting the major part of the required circuitry into a common section where it may be shared by all channels. This objective is achieved by using a digital PLL as an FM demodulator with low cost logic circuits located in the channel units and clocks with their associated driving amplifiers located in the common circuits. PLL's which use analog circuits have received considerable attention and analysis and synthesis methods 2207 2208 T H E BELL SYSTEM TECHNICAL JOURNAL, DECEMBER 1968 are available. 1 , 2 However, the circuits covered here are digital, and the approach is similar to t h a t of digital (or sampled-data) filters. 3, 4 By using a digital PLL, no low-pass filter or voltage-controlled oscillator, generally associated with the feedback loop of conventional PLL's is required.* This property, along with high stability and the absence of adjustments makes the digital PLL ideal for microminiaturization using monolithic integrated circuits. This paper presents snythesis procedures for an nth order digital PLL. The PLL realized by such a procedure possesses a response which obeys a linear ?ith order difference equation. Analysis is performed using 7J transform methods commonly encountered in sampleddata control systems.