Attachment Reliability of Chip Scale Packages with Various Constructions

Attachement reliability was identified early as an impediment to the full realization of the predicted board real estate benefits of Chip Scale packages (CSP). This is especially true for the high-end telecommunication equipment that requires very high reliability for over ten years of service. To address this issue, many device vendors and packaging companies have experimented with different constructions to increase the package overall coefficient of thermal expansion in order to reduce the mismatch with FR-4, the electronic industries' predominant PWB material. Constructions that increase the overall package CTE or decouple the low CTE silicon from the solder joints have lead to improved CSP attachment reliability. With such constructions, some of the evlauted chip scale packages met the attachment reliability requirement for high-end telecommunication equipment. However, many CSP packages still have lower attachment reliability than is needed for these products. All the already established reliability drivers for the early area array packages are shown to hold true for the fine pitch CSPs. The low CSP attachment reliability results are made even lower when mirror image design is employed to gain further densification of circuit packs.