BIST for Embedded RAMs, ROMs and PLAs in Custom VLSI

A Built-In Self Test (BIST) approach for testing RAMs, ROMs, and PLAs embedded in VLSI devices is presented along with data regarding the resulting 3 percent to 5 percent increase in chip size. With this approach, vertical testability can be achieved along with a significant reduction in testing time and complexity at the device, circuit pack, and system level.