Cache-Friendly IP Reassembly Network Function
03 March 2020
In the emerging SD-WAN environments, network packets are heavily encapsulated to support various policy-driven network slices and secure connectivity. While such heavy encapsulation increases the chance of IP fragmentation in SD-WAN traffic, existing mechanisms to avoid IP fragmentation such as path MTU discovery, TSO/GSO and pre-fragmentation are often not sufficient. This makes IP reassembly an important ingredient of the SD-WAN architecture, and maximizing its processing efficiency is one of critical design criteria in resource-constrained SD-WAN gateways. In this paper, we show that the state-of-the-art software implementation of IP reassembly does not utilize underlying hardware caches effectively, and in turn re-architect IP reassembly to make it more cache-friendly. The new design leverages well-known software engineering techniques such as loop fission, loop unrolling and prefetch-friendly data structures. Using prototype implementation, we show that the re-designed IP reassembly can support 25-35% higher packet processing throughput than the state-of-the-art implementation.
