Challenges of Gate-Dielectric Scaling, including the Vertical Replacement-Gate MOSFET

The Vertical, Replacement-Gate (VRG) process makes Si MOSFETs with all critical dimensions independent of lithography. The process combines (1) gate length controlled precisely through a film thickness, independent of lithography and etch (2) high-quality gate oxide grown on single-crystal Si, and (3) self-aligned source and drain extensions. These are achieved with current manufacturing tools and techniques. The first devices included 200 nm gate-length devices with more drive current than conventional devices while maintaining off current, and 50 nm devices, which are the smallest made without using exotic techniques for narrow line widths. The process can be extended to a complete CMOS process only modestly more complex than the current planar process. The circuit density is similar for planar and VRG CMOS, limited primarily by lithography. VRG CMOS should be faster than planar, due to reduced junction capacitance and increased drive current per unit area. Moreover, this process provides a manufacturable platform for future innovations in CMOS devices. This work was done in close collaboration with Jack Hergenrother and supported by many experts in Physical Sciences Research at Bell Labs in Murray Hill, NJ