Comparison of B and BF sub 2 source/drain Extensions Implants for PMOS Transistors with Thin Gate Oxides

In dual-doped polysilicon process both NMOS and PMOS devices have surface channel operation, which reduces short channel effect. This process also provides the low and symmetric threshold voltages, which are required to operate at lower power supply voltages. One of the challenges for dual poly process is that boron from the p-type polysilicon gate electrode can diffuse through the gate dielectric layer and into the channel region during dopant activation. This causes a shift in the threshold and flat band voltages of the device and reduces process control. It is known that BF sub 2 gate implants result in more B penetration through the gate as compared to the B gate implants for a given anneal ing condition. In this paper we investigate the effect of fluorine in BF sub 2 source/drain extensions implants on PMOS transistor parameters.