Ilija Hadzic
Murray Hill, NJ, USA
Biography
Ilija Hadzic grew up in a place that is now known as Serbia, a small country located in the Balkans region of Europe, known mostly for basketball and tennis players and less for other more important things. He spent half of his youth on dry land hacking various computers, most of which can now only be found in museums or junk yards. The other half, he spent on water, rowing in various crews and competing against other crews.
Ilija spent the last decade of the previous century in a quest for pieces of paper that would make his knowledge about computer software and hardware official. The highest one he got his hands on was a PhD degree in Electrical Engineering from the University of Pennsylvania, about a year before the turn of the century. Armed with the knowledge, optimism, and degrees, Ilija successfully convinced a few guys in Murray Hill, New Jersey that they should pay him for what he would do anyway as his hobby. So he was issued a badge with a red logo that looked like a coffee stain and put in a nice office (with a window) at the end of the hallway.
Ilija would spend the next decade coming up with all kinds of cool hardware and software that would eventually be put in some dark rooms and wired up into a network that everyone takes for granted, but very few appreciate how difficult it is to make it work. Along the way, he wrote a bunch of papers and patents about the stuff he was doing and above all had a lot of fun. Although Ilija has remained in the same office though the present day, the name of the corporation that rented his brain, body and soul got longer and the logo on his badge changed into something that looked like a purple Mobius strip.
One morning Ilija woke up thinking that it may be cool to try out something other than coming up with a next great method to send "Mr. Watson come here, I need you." from one end of the wire to the other. Those who wrote his paychecks didn't mind, so Ilija started experimenting with graphics, video, virtual machines, and web applications. He is currently having fun building large and complex software systems and doing cool things with them.
Besides firing his synapses at insane rate, Ilija also keeps his muscles from rusting by running from one end of a grass field to the other while kicking a spherical object filled up with pressurized air. When it's too cold for that, he opts for sliding down a snow-covered hill while standing on two pieces of polished plywood. Ilija shares his home in New Jersey with the nicest and the most beautiful person in the world, who is about his age and does not mind coping with his geekyness, along with two younger persons who carry half of his DNA code.
- PhD, Electrical Engineering, University of Pennsylvania, 1999
- M.S., Electrical Engineering, University of Pennsylvania, 1996
- B.S., Electrical Engineering, University of Novi Sad, 1995
- I. Hadzic, H.C. Woithe and M. D. Carroll, A Simple Desktop Compression and Streaming System, IEEE International Symposium on Multimedia, Anaheim, California, December 2013
- M.D. Carroll, I. Hadzic and W.A. Katsak, 3D Rendering in the Cloud, Bell Labs Technical Journal, vol. 17, no. 2, pp. 55-66, September, 2012.
- I. Hadzic, D. R. Morgan and Z. Sayeed, A Synchronization Algorithm for Packet MANs, IEEE Transactions on Communications, vol. 59, no. 4, pp. 1142-1153, Apr 2011.
- I. Hadzic and D. R. Morgan, Dynamic Packet Selection for Clock Recovery, IEEE International Symposium on Precision Clock Synchronization (ISPCS), Portsmouth, New Hampshire, October 2010.
- D. R. Morgan and I. Hadzic, Non-uniform Linear Regression with Block-Wise Sample-Minimum Preprocessing, IEEE Transactions on Signal Processing, vol. 58, no. 8, pp. 4040-4049, Aug. 2010.
- D. R. Morgan and I. Hadzic, A Simple Analysis of Linear Regression with Sample-Minimum Erlang variates, IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP), Dallas, Texas, March 2010.
- B. Mochizuki and I. Hadzic, Improving IEEE 1588v2 clock performance through controlled packet departures, IEEE Communications Letters, vol. 14, no. 5, pp. 459-461, May 2010.
- I. Hadzic and D. R. Morgan, On Packet Selection Criteria for Clock Recovery, IEEE International Symposium on Precision Clock Synchronization (ISPCS), Brescia, Italy, October 2009.
- C. Soviani, I. Hadzic and S. A. Edwards, Synthesis and Optimization of Pipelined Packet Processors, IEEE Transactions on Computer-Aided Design (TCAD), vol. 28, no. 2, pp. 231-244, Feb. 2009.
- C. Soviani, I. Hadzic and S. A. Edwards, Synthesis of High-Performance Packet Processing Pipelines, ACM Design Automation Conference, San Francisco, California, July 2006.
- D. Suvakovic and I. Hadzic, An FPGA Application with High Speed Serial Transceiver Running at Sub-nominal Rate, FPL2005, Tampere, Finland, August 2005.
- I. Hadzic and E. S. Szurkowski, High-Performance Synchronization for Circuit Emulation in an Ethernet MAN, Journal of Communications and Networks, vol. 7, no. 1, pp 1-12, Jan. 2005.
- I. Hadzic and J. M. Smith, Balancing Performance and Flexibility with Hardware Support for Network Architectures, ACM Transactions of Computer Systems, vol. 21, no. 4, pp. 375-411, Nov 2003.
- I. Hadzic, Hierarchical MAC Address Space in Public Ethernet Networks, IEEE Globecom 2001, San Antonio, Texas, November 2001.
- I. Hadzic, S. Udani and J. M. Smith, FPGA Viruses, 9th International Conference on Field Programmable Logic and Applications (FPL 99), Glasgow, Scotland.
- I. Hadzic, J. M. Smith and W. S. Marcus, On-the-fly Programmable Hardware for Networks, IEEE Globecom, Sydney, Australia, November 1998.
- W. S. Marcus, I. Hadzic, A. J. McAuley and J. M. Smith, Protocol Boosters: Applying Programmability to Network Infrastructures, IEEE Communications Magazine, October 1998.
- J. M. Smith, I. Hadzic and W. S. Marcus, ACTIVE Interconnects: Let's have some guts, Hot Interconnects Conference, Palo Alto CA, August 1998.
- I. Hadzic and J. M. Smith, P4: A platform for FPGA implementation of Protocol Boosters, FPL 97, London UK, September 1997.
- Method, apparatus, and system for frequency synchronization between devices communicating over a packet network, US Patent No. 8,300,749.
- Frequency synchronization using first and second frequency error estimators, US Patent No. 8,275,087.
- Apparatus for enhancing packet communication, US Patent No. 7,928,866.
- High-speed serial transceiver with sub-nominal rate operating mode, US Patent No. 7,672,416.
- Software-hardware partitioning of a scheduled medium-access protocol, US Patent No. 7,525,971.
- System and method for synchronization in asynchronous transport networks, US Patent No. 7,372,875.
- Ethernet packet encapsulation for metropolitan area Ethernet networks, US Patent No. 7,130,303.
- Clock, Data and Time Recovery using Bit-Resolved Timing Registers, US Patent No. 7,123,675.
Peer reviewer:
- IEEE Communication Magazine
- Communications of the ACM
- IEEE Transactions on Communications
- IEEE Communications Letters
- IEEE LANMAN Conference
Technical Program Committee Member:
- ACM/IEEE ANCS 2014
- ACM/IEEE ANCS 2015
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