Automatic video editing is a hot topic because of the rapid growth of video.
In this paper, we present a framework for planning and executing performance and resiliency testing of SDN.
A digitally trimmable 100 MHz double ramping multivibrator that is insensitive to temperature and power supply variations has been realized in a 0.9micron CMOS process.
A continuous-time forward equalizer with one adaptive zero and a seventh-order linear-phase low-pass filter are described.
We designed and tested a VLSI chip implementing a connectionist model of a neural network.
We designed and tested a collective computing associative memory chip with an architecture based on a model for a neural network.
No abstract provided.
We describe a CMOS VLSI chip with an architecture based on a connectionist model for neural networks.
A 125Mbaud quad transceiver for 10/100 fast ethernet has been designed in a 5V 0.35micron digital CMOS process. Power consumption for the device is 3W.
A mixed analog/digital chip that forms the core of a medium- speed modem for use on the public switched telephone network is described.
