DESCRIPTION O F T H E A N T E N N A The antenna is a 60-foot diameter paraboloid made up of forty-eight radial sectors, each constructed of sheet aluminum.
This paper describes a programmable 16-bit fixed point Digital Signal Processor (DSP) instruction cycle time of 60 ns.
After the A|RT-Library and A|RT-Builder, two very useful tools for designing hardware structures using ANSI-C constructs, Frontier Design now offers with their new product A|RT-Designer a tool that
This paper presents a 64-element 28-GHz phased-array transceiver for 5G communications based on 2x2 transmit/receive (TRX) beamformer chips.
A 64x17 cross point switch has been developed for switching high-speed telephone lines in central office applications.
This paper presents a highly integrated wideband linear receiver with on-chip active frequency doubler implemented in a low-cost 200/180 GHz fT/fmax 0.18 μm SiGe BiCMOS technology.
Very high-speed digital subscriber line (VDSL) technology can deliver data at multi-Mbits/s over the unshielded, twisted pair in overlay to the plain old telephone service (POTS) and ISDN services.
In this paper we present a design for an 8 bit x 8 bit parallel pipeline multiplier for high-speed digital signal processing applications. The multiplier is pipelined at the bit level.
A transmitter and receiver phased array chipset is demonstrated in the range between 70 and 100GHz using a 0.18&μm SiGe BiCMOS process with fT / fMAX of 240/270GHz.
