The crystal structure of CeO sub 2 has been investigated to 70 GPa using energy dispersive x-ray diffraction in a diamond anvil cell.
This paper describes the design and VLSI implementation of a signal chip fourth order recursive digital filter for sample rates up to 100 MHz.
A 6x6 bit parallel multiplier was designed in Self-Aligned GaAs/AlGaAs Heterostructure FETs for demonstrating design and fabrication capabilities of an LSI GaAs pilot production line.
A 6x6 bit parallel multiplier has been implemented in the 1- um Self-Aligned GaAs/AlGaAs Heterostructure FET (HFET) technology to demonstrate the design and fabrication capabilities of an LSI GaAs
A high performance 1024 x 1 bit static random access memory (RAM) has been designed and fabricated using an epitaxial GaAs direct coupled logic (DCFL) process.
In recent years, considerable research had been conducted on the formulation and development of high-speed B-ISDN switch architectures which are capable of supporting a variety of applications [3],
The thesis describes the design of a high speed first order oversampled sigma-delta modulator that can be used as part of a Digital-to- Analog converter.
This paper describes the design of a centralized controller/scheduler for a communication switch with a banyan switching fabric built using unbuffered switches.
This paper reports on an ideal device structure for integrating high speed bipolar and CMOS. Both the vertical NPN and MOS devices have super self-aligned structures.
A miniature coax circuit incorporating a sensitive InGaAs PIN and a picosecond photoconductor is described.
