A 5-b flash ADC with a closed-loop THA is implemented in 0.18-mum SiGe BiCMOS.
A 256 bit GaAs SRAM has been designed that incorporates laser programming to allow any defective row or column to be replaced with a spare row or column.
This paper describes a silicon receiver for a multiple-input multiple-output (MIMO) wireless channel that supports up to 28.8 Mb/s using a 4x4 QPSK configuration over a 5 MHz frequency selective ch
We describe a receiver for HSDPA supporting up to 28.8 Mbps using QPSK over a 5 MHz frequency selective 4x4 MIMO wireless channel (5.76 bits/s/Hz).
The reaction of 1,3-bis(tetrazol-1-yl)-2-propanol (btzpol) with Fe(BF4)(2) center dot 6H(2)O in acetonitrile yields the remarkable 2D coordination polymer {[}Fe-II(btzpol)(1.8)(btzpol-OBF3)(1.2)](B
An optical receiver front-end for SONET OC-48 (2.5 Gb/s) is shown.
A multiprocessor DSP chip with four programmable processing elements and a global resource controller connected to a high performance split-transaction bus is reported.
A clock signal embedded in a NRZ (Non Return to Zero) 2 sup (31) -1 pseudo-random data stream is used to injection lock a slave CMOS LC tank circuit.
We describe in this paper a monolithic integrated circuit implementing a full-duplex 300 bauds modem function. This I.C. can either meet the CCITT V21 staandard or BELL 103 standard.
In this paper, a fully passivated InP/GaAsSb/InP DHBT on InP substrate with excellent DC and RF performance is developed.
