A 112 GS/s 1-to-4 ADC front-end in IHP 130 nm SiGe BiCMOS based on charge sampling is presented.
Voltage-mode sampling circuits operating at mm-wave frequen-cies require clocks with root-mean-squared (RMS) jitter in the two-digit femtosecond range for high SNR performance.
A 12Gb/s analog link is experimentally demonstrated using a linear high-power Externally Modulated Laser and six IFoF-channels over 25km-fiber and 5m V-band, forming the record capacity-distance in
In SONET, a limiting amplifier amplifies the voltage output of the transimpedance amplifier to a level high enough for a decision circuit to determine correct 1s and 0s from incoming bit streams.
This paper presents the design of a very low power 12-bit 650-MSps time-interleaved pipeline analog-to-digital converter (ADC) for digital beam forming applications.
The time-varying effects of Polarization Mode Dispersion (PMD) and other fiber distortions cause the performance degradation of fiber optic transmission at 10-Gb/s and beyond.
Optical techniques have the potential to overcome speed limitations for digital-to-analog conversion.
To enable 40Gb/s data transmission over optical fibres using QPSK modulation, the first step of the receiver signal-processing pipeline is a 128-tap FIR filter that compensates the chromatic disper
This paper describes a capacitor error-averaging technique to implement a high- resolution pipelined ADC, which exhibits a 12 bit linearity at a 1 MHz sampling rate.
A Sigma-Delta A/D converter which achieves 81 dB of resolution, 86 DB of linearity and produces output samples at 80 kHz is described.
