We report the first complementary clocked frequency divider using dual gate Selectively Doped Heterostructure Transistors (SDHT).
A CDR circuit dedicated to satellite embedded data link is presented. This circuit combines an injection locked oscillator, with a phase alignment circuit, to achieve the clock recovery.
This paper presents a single-chip eye opening monitor IC for decision-guided optimization of the frequency response of an optical receiver, The IC provides an analog output voltage proportional to
I M P A T T diodes provide a practical means of generating watts of cw microwave power. These devices are now commonly used in transmitter power amplifiers at 6 GHz and higher frequencies.
This paper reports the design and measurement results of a 1-tap feed-forward based analog equalizer, mainly designed with differential pair amplifier cells composed of Indium Phosphide (InP) heter
We demonstrate a WDM system with 1021 independent wavelength channels within the C- and L-bands of the EDFA. All channels carry RZ data at 74 Mb/s and are spaced by only 9.5 GHz.
A novel 107-Gbit/s opto-electronic receiver has been designed using hybrid integration of a photodiode and electronic demultiplexer.
A novel 107-Gbit/s optoelectronic receiver has been designed using hybrid integration of a photodiode and electronic demultiplexer.
A monolithic CMOS circuit that can recover the clock and decode 10Mb/s Manchester data into NRZ data has been developed.
A phase-invariant variable-gain PA RFIC in 130-nm SiGe BiCMOS supporting multi-QAM waveforms over the entire D-band (110?170 GHz) is presented.
