A novel 107-Gbit/s optoelectronic receiver has been designed using hybrid integration of a photodiode and electronic demultiplexer.
A monolithic CMOS circuit that can recover the clock and decode 10Mb/s Manchester data into NRZ data has been developed.
A phase-invariant variable-gain PA RFIC in 130-nm SiGe BiCMOS supporting multi-QAM waveforms over the entire D-band (110?170 GHz) is presented.
A 112 GS/s 1-to-4 ADC front-end in IHP 130 nm SiGe BiCMOS based on charge sampling is presented.
Voltage-mode sampling circuits operating at mm-wave frequen-cies require clocks with root-mean-squared (RMS) jitter in the two-digit femtosecond range for high SNR performance.
A 12Gb/s analog link is experimentally demonstrated using a linear high-power Externally Modulated Laser and six IFoF-channels over 25km-fiber and 5m V-band, forming the record capacity-distance in
In SONET, a limiting amplifier amplifies the voltage output of the transimpedance amplifier to a level high enough for a decision circuit to determine correct 1s and 0s from incoming bit streams.
This paper presents the design of a very low power 12-bit 650-MSps time-interleaved pipeline analog-to-digital converter (ADC) for digital beam forming applications.
A capacitor error averaging technique is applied to perform an accurate multiply-by-two (x2) function required in high- resolution pipelined analog-to-digital (A/D) converters.
The time-varying effects of Polarization Mode Dispersion (PMD) and other fiber distortions cause the performance degradation of fiber optic transmission at 10-Gb/s and beyond.
