We report the design and measurement of a differential distributed driver amplifier integrated with a 2:1selector, realized in a 320/380-GHz FT/FMAX 0.7-µm InP technology.
A monolithic CMOS voltage-controlled oscillator (VCO) incorporates two identical fixed-frequency LC oscillators coupled in a ring topology to generate a variable-frequency output by varying the cou
This paper will describe a programmable 16-bit fixed point Digital Signal Processor with an instruction cycle time of 60 ns.
DESCRIPTION O F T H E A N T E N N A The antenna is a 60-foot diameter paraboloid made up of forty-eight radial sectors, each constructed of sheet aluminum.
This paper describes a programmable 16-bit fixed point Digital Signal Processor (DSP) instruction cycle time of 60 ns.
We report on a C+L-band transmission of 62 Tb/s over 6600km using 49 GBd probabilistically-shaped 64QAM (PS64QAM) modulation format, digital-back propagation based nonlinear compensation, and adapt
After the A|RT-Library and A|RT-Builder, two very useful tools for designing hardware structures using ANSI-C constructs, Frontier Design now offers with their new product A|RT-Designer a tool that
This paper presents a 64-element 28-GHz phased-array transceiver for 5G communications based on 2x2 transmit/receive (TRX) beamformer chips.
A 64x17 cross point switch has been developed for switching high-speed telephone lines in central office applications.
This paper presents a highly integrated wideband linear receiver with on-chip active frequency doubler implemented in a low-cost 200/180 GHz fT/fmax 0.18 μm SiGe BiCMOS technology.
