The high performance CMOS transmitter-receiver chip consists of two functionally independent sections which can simultaneously transmitter section receives byte-wide datum at 40MB/s and transforms
A bandpass Sigma-Delta modulator is described in this paper that uses frequency translation inside the Sigma-Delta modulator loop to take advantage of the attributes of both continuous-time and dis
We demonstrate a 40-Gb/s hybrid CWDM-TDM PON with a novel remote node including a cyclic CWDM multiplexer/demultiplexer.
We have demonstrated a record sensitivity of -36.9 dBm (39 photons/bit) for a BER of 10-9 at 42.7-Gb/s using an integrated balanced optical front end.
We have demonstrated a record sensitivity of -36.9 dBm (39 photons/bit) for a BER of 10 sup -9 at 42.7-Gb/s using an integrated balanced optical front end.
A monolithic 45 MHz CMOS phase/frequency-locked loop circuit for timing recovery that can capture and lock over a +/-30% initial frequency offset range has been developed.
We describe the development of a 48 GHz fully integrated differential VCO, using InP/ InGaAs double heterojunction bipolar transistors (DHBTs), for 40 Gbit/ s optical communication systems.
We describe the development of a 48 GHz fully integrated differential VCO, using InP/InGaAs double heterojunction bipolar transistors (DHBTs), for 40 Gbit/s optical communication systems.
We report on the development of an NMOS 2.1 frequency divider circuit that operates to over 5 GHz. It is powered from a 2.5 Volt supply and dissipates only 0.012 Watt.
In this paper, we present a 5-b fully differential, flash-type ADC with data update rate over 10 GS/s processed in SiGe BiCMOS technology.
