We designed and tested a VLSI chip implementing a connectionist model of a neural network.
We designed and tested a collective computing associative memory chip with an architecture based on a model for a neural network.
We describe a CMOS VLSI chip with an architecture based on a connectionist model for neural networks.
A 125Mbaud quad transceiver for 10/100 fast ethernet has been designed in a 5V 0.35micron digital CMOS process. Power consumption for the device is 3W.
A mixed analog/digital chip that forms the core of a medium- speed modem for use on the public switched telephone network is described.
This paper describes two CMOS resistive ring mixer MMICs for GSM 900 and DCS 1800 base station applications.
A programmable phase-locked-loop (PLL)-based frequency synthesizer, capable of automatically adjusting the nominal center frequency of the voltage-controlled oscillator (VCO) to an optimum value is
We propose an efficient method to deal with the matching and registration problem found in cross-source point clouds captured by different types of sensors.
With the development of numerous 3D sensing technologies, object registration on cross-source point cloud has aroused researchers' interests.
Currently, several systems are being considered for digital audio broadcasting (DAB) and some of these systems will be deployed for commercial use in the near-future.
